System for improved memory cell access
April 18, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesGate stress test of a MOS memory CMOS bootstrapped output driver method and circuit Semiconductor memory device with circuit for isolating arrayed memory cells, and method for isolating Boosting clamping circuit and output buffer circuit using the same Method and apparatus for providing a faster ones voltage level restore operation in a dram CMOS bootstrapped output driver method and circuit Nonvolatile semiconductor memory device capable of preventing read error caused by overerase state and method therefor Enhancement circuit and method for ensuring diactuation of a switching device Bootstrapped high-speed output buffer Non-volatile semiconductor memory device InventorApplicationNo. 999865 filed on 04/18/1997US Classes:365/230.06, Particular decoder or driver circuit365/189.09Including reference or bias voltage generatorExaminersPrimary: Nelms, David C.Assistant: Ho, Hoai Attorney, Agent or FirmInternational ClassG11C 008/00AbstractA voltage booting circuit for booting the switching signal applied to a column access passgate is employed to reduce the voltage drop across the passgate. Reduction of the voltage dropped across the passgate results in faster read and write times and improved noise margin. In one application the booted voltage is used only during a write operation, but not during a read. In another application, the booted voltage is used during both operations. | |
