Integrated thermoelectric cooler formed on the backside of a substrate
Patent 5956569 Issued on September 21, 1999. Estimated Expiration Date: 
October 24, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 24, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesArrangement with several thermal elements in series connection Multilayer film multijunction thermal converters Microelectronic thermoelectric device and systems incorporating such device Patent #: 5837929 InventorsAssigneeApplicationNo. 957677 filed on 10/24/1997US Classes:438/48, MAKING DEVICE OR CIRCUIT RESPONSIVE TO NONELECTRICAL SIGNAL136/200, THERMOELECTRIC136/201, Processes136/203, Peltier effect device136/204, Including additional heat exchange means136/225, Having strip, film or plate-type thermocouples136/228, One junction element surrounded by another junction element136/293, Circuits257/E23.082, Cooling arrangements using Peltier effect (EPO)361/718, For integrated circuit438/54, Thermally responsive438/55, Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor438/612, Forming solder contact or bonding pad438/928FRONT AND REAR SURFACE PROCESSINGExaminersPrimary: Booth, Richard A.Assistant: Zarneke, David A. Attorney, Agent or FirmInternational ClassH01L 021/00AbstractThe present invention provides a structure and a method of fabricating a thermoelectric Cooler directly on the backside of a semiconductor substrate. The thermoelectric (TE) cooler (thermoelectric cooler) disperses heat from an integrated circuit (IC) that is formed on the front-side of the silicon substrate. Spaced first bonding pad holes 28 are formed in the backside of a substrate that expose bonding pads 24. Second holes 32 are formed between the spaced first bonding pad holes 28. A first insulating layer 34 is formed over the backside of the substrate, but not over the bonding pad 24. A metal layer is formed lining the first bonding pad holes 28. A polysilicon layer 46 is formed over the surface of the backside of the substrate in the second holes. The polysilicon layer is implanted thereby forming alternating adjacent N and P doped sections 46p 46n in the second holes. The adjacent N and P doped polysilicon sections 46n 46p are electrically connected to the bonding pads 24 by the metal layer 38.Field of SearchMAKING DEVICE OR CIRCUIT RESPONSIVE TO NONELECTRICAL SIGNALThermally responsive Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor Forming solder contact or bonding pad FRONT AND REAR SURFACE PROCESSING For integrated circuit Peltier effect device Including additional heat exchange means Processes Circuits Having strip, film or plate-type thermocouples One junction element surrounded by another junction element THERMOELECTRIC | |
