Multiprocessor system and its control method
December 19, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesFault detection and redundancy management system Address conversion unit for multiprocessor system Multiprocessor system having a shared memory for enhanced interprocessor communication Processor-selection system Methods for efficient distribution of parallel tasks to slave processes in a multiprocessing system Initialization system for a close-coupled multiprocessor system Method and apparatus for independently resetting processors and cache controllers in multiple processor systems Method of booting a multiprocessor computer where execution is transferring from a first processor to a second processor based on the first processor having had a critical error Processor element having a plurality of processors which communicate with each other and selectively use a common bus Method and apparatus for initializing a multiprocessor system while resetting defective CPU's detected during operation thereof Patent #: 5583987 InventorsAssigneeApplicationNo. 995000 filed on 12/19/1997US Classes:713/1, DIGITAL DATA PROCESSING SYSTEM INITIALIZATION OR CONFIGURATION (E.G., INITIALIZING, SET UP, CONFIGURATION, OR RESETTING)709/208, MASTER/SLAVE COMPUTER CONTROLLING709/209, Master/slave mode selecting712/31, Master/slave714/13Prepared backup processor (e.g., initializing cold backup) or updating backup processor (e.g., by checkpoint message)ExaminersPrimary: Palys, Joseph E.Assistant: Mai, Rijue Attorney, Agent or FirmForeign Patent References
International ClassesG06F 009/445G06F 015/00 Foreign Application Priority Data1994-01-28 JPAbstractOne of processors connected effectively to a system is allocated to a master processor and the other remaining processors are allocated to slave processors. Each processor compares the self processor number of a processor number register and the processor number of the other processor of a processor effective register. For example, when the self processor number is smallest as compared with the other processor numbers, it is recognized that the self processor is a master processor. A master initialization diagnosing process after completion of the allocation is monitored by the slave processor. When an abnormality of the master processor is recognized, a degeneration to disconnect the master processor from the system is executed and is again reconstructed by the allocating process of master/slaves. Even when an abnormality occurs in the master processor, the operation in which the system was degenerated can be executed until the minimum construction in which two or more processors normally operate.Field of SearchCachingResetting processor Prepared backup processor (e.g., initializing cold backup) or updating backup processor (e.g., by checkpoint message) DIGITAL DATA PROCESSING SYSTEM INITIALIZATION OR CONFIGURATION (E.G., INITIALIZING, SET UP, CONFIGURATION, OR RESETTING) MASTER/SLAVE COMPUTER CONTROLLING Master/slave mode selecting Master/slave | |
