Variable work function transistor high density mask ROM
Patent 5942786 Issued on August 24, 1999. Estimated Expiration Date: 
December 17, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 17, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of manufacturing a reference voltage generator device Semiconductor device Semiconductor device having two-level wiring Semiconductor floating gate device having improved channel-floating gate interaction Semiconductor device having a buried channel transistor Patent #: 5536962 InventorsApplicationNo. 767824 filed on 12/17/1996US Classes:257/390, Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM))257/401, With specified physical layout (e.g., ring gate, source/drain regions shared between plural FETs, plural sections connected in parallel to form power MOSFET)257/407, With gate electrode of controlled workfunction material (e.g., low workfunction gate material)257/413, Polysilicon laminated with silicide257/E27.102Read-only memory, ROM, structure (EPO)ExaminersPrimary: Chaudhuri, OlikAssistant: Weiss, Howard Attorney, Agent or FirmInternational ClassesH01L 029/76H01L 029/94 H01L 031/062 H01L 031/113 AbstractA mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped P-type and then an encoding mask is formed, with openings in the encoding mask exposing regions of the polysilicon to be formed into gates of FETs with low threshold voltages. Either arsenic or phosphorus is doped into the polysilicon through the mask openings. The mask is removed, a layer of conductive material such as tungsten silicide is deposited and the polysilicon and the conductive material are formed into word lines for the ROM. The word lines of the ROM serve as gates for the FETs and the bit lines serve as sources and drains for the FETs.Field of SearchGate electrode consists of refractory or platinum group metal or silicideMatrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM)) With specified physical layout (e.g., ring gate, source/drain regions shared between plural FETs, plural sections connected in parallel to form power MOSFET) With gate electrode of controlled workfunction material (e.g., low workfunction gate material) Gate electrode of refractory material (e.g., polysilicon or a silicide of a refractory or platinum group metal) Polysilicon laminated with silicide With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction) | |
