Semiconductor ESD protection circuit
Patent 5940258 Issued on August 17, 1999. Estimated Expiration Date: 
February 5, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
February 5, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesOutput buffer with improved ESD protection Method of forming an electrostatic discharge protection circuit Electrostatic discharge suppression circuit employing low-voltage triggering silicon-controlled rectifier Patent #: 5528188 InventorAssigneeApplicationNo. 795435 filed on 02/05/1997US Classes:361/56, Voltage responsive257/355With overvoltage protective meansExaminersPrimary: Medley, Sally C.Attorney, Agent or FirmInternational ClassH02H 009/04AbstractProtection circuitry (10) for protecting an integrated circuit from an ESD pulse is provided. The protection circuitry (10) includes discharge circuitry (14) on a substrate (11) that discharges an ESD pulse to the integrated circuit to ground (18). The protection circuitry (10) also includes a substrate bias generator (25) that uses a portion of the ESD pulse's energy to bias the substrate (11) of the discharge circuitry (14). | |
