Multiprocessor arrangement including bus arbitration scheme involving plural CPU clusters that address each other as "phantom" CPUs
Patent 5935230 Issued on August 10, 1999. Estimated Expiration Date: 
July 9, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 9, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesInitialization mechanism for symmetric arbitration agents Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses Arrangement for expanding the device capacity of a bus Patent #: 5596727 InventorsAssigneeApplicationNo. 890515 filed on 07/09/1997US Classes:710/111, Rotational prioritizing (i.e., round robin)708/230, Multifunctional710/100, INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING)710/107, Bus access regulation710/113, Centralized bus arbitration710/114, Static bus prioritization711/157, Interleaving712/1, PROCESSING ARCHITECTURE712/3, Scalar/vector processor interface712/11, Array processor element interconnection712/15, Reconfiguring712/16Array processor operationExaminersPrimary: Sheikh, Ayaz R.Assistant: Jean, Frantz B. Attorney, Agent or FirmInternational ClassG06F 013/14AbstractAt least two clusters of CPUs are present in a multiprocessor computer system. Each CPU cluster has a given number of CPUs, each CPU having an associated ID such as an ID number. An additional ID number, not associated with a CPU in the same cluster, is associated with the opposite CPU cluster that appears to the original cluster as a "phantom" processor. A round-robin bus arbitration scheme allows ordered ownership of a common bus within a first cluster until the ID reaches the "phantom" processor, at which time bus ownership passes to a CPU in the second cluster. This arrangement is preferably symmetric, so that when a CPU from the first cluster requests ownership of the bus, it is granted bus ownership by virtue of the first cluster's appearance to the second cluster as a "phantom" CPU.Other References
Field of SearchInterleavingRotational prioritizing (i.e., round robin) INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING) Bus access regulation Centralized bus arbitration Static bus prioritization Array processor element interconnection Reconfiguring Array processor operation Scalar/vector processor interface PROCESSING ARCHITECTURE | |
