Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array
January 22, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor memory cell Non-volatile semiconductor memory device Erasable electrically programmable read only memory cell using trench edge tunnelling Tunnel injection controlling type semiconductor device controlled by static induction effect Non-volatile semiconductor memory device and method of the manufacture thereof Three-dimensional memory cell with integral select transistor Floating gate memory cell and device Dram cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof Dram with a vertical capacitor and transistor 5016067 Inventors
ApplicationNo. 792955 filed on 01/22/1997US Classes:257/306, Stacked capacitor257/296, Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)257/302, Vertical transistor257/303, Stacked capacitor257/E21.652, In combination with vertical transistor (EPO)257/E21.655, Transistor in U- or V-shaped trench in substrate (EPO)257/E21.657, Making bit line (EPO)257/E21.659, Making word line (EPO)257/E21.68, Electrically programmable (EPROM), i.e., floating gate memory structures (EPO)257/E27.103, Electrically programmable ROM (EPO)438/248, Including isolation means formed in trench438/386, Trench capacitor438/396Stacked capacitorExaminersPrimary: Martin-Wallace, ValenciaAttorney, Agent or FirmForeign Patent References
International ClassesH01L 029/108H01L 029/76 AbstractA densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.Other References
Field of SearchInsulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)Vertical transistor Stacked capacitor Stacked capacitor Trench capacitor Having stacked capacitor structure (e.g., stacked trench, buried stacked capacitor, etc.) Stacked capacitor Including isolation means formed in trench | |
