Programmable logic array circuits comprising look up table implementation of fast carry adders and counters
August 19, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProgrammable array logic circuit Conditional carry techniques for digital processors Special interconnect for configurable logic array Configurable logic element ALU operation: modulo two sum Microprocessor oriented configurable logic element Programmable logic array for carrying out logic operations of binary input signals Configurable electrical circuit having configurable logic elements and configurable interconnects Programmable logic array having feedback flip-flops connected between a product array's inputs and its outputs Programmable logic array circuit having a gate to control an output condition state of a latch thereof InventorsApplicationNo. 136317 filed on 08/19/1998US Classes:326/40, With flip-flop or sequential device326/39, Array (e.g., PLA, PAL, PLD, etc.)326/41Significant integrated structure, layout, or layout interconnectionsExaminersPrimary: Tokar, MichaelAssistant: Chang, Daniel D. Attorney, Agent or FirmForeign Patent References
International ClassH03K 019/177AbstractA programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. Look up tables for use in programmable logic devices are modified to facilitate use of those tables to provide adders (including subtracters) and various types of counters. Each look up table is effectively partitioned into smaller look up tables when an adder or counter is required. One portion of the partitioned table is used to provide a sum out signal, while the other portion of the partitioned table is used to provide a fast carry out signal for application to the next stage of the adder or counter.Other References
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