Method for forming dense multilevel interconnection metallurgy for semiconductor devices
Method of forming an RIE etch barrier by in situ conversion of a silicon containing alkyl polyamide/polyimide
Pattern forming method
Method for fabricating an insulating film from a silicone resin using O.sub .
Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric
Process for fabricating an integrated circuit device by forming a planarized polysilazane layer and oxidizing to form oxide layer
Coating electronic substrates with silica derived from silazane polymers
Process for fabricating a device
Global planarization using a polyimide block
Silylated photo-resist layer and planarizing method Patent #: 5756256
ApplicationNo. 801328 filed on 02/18/1997
US Classes:438/623, Including organic insulating material between metal levels257/E21.259, Organic layers, e.g., photoresist (EPO)257/E21.576, Characterized by formation and post treatment of dielectrics, e.g., planarizing (EPO)438/780, Depositing organic material (e.g., polymer, etc.)438/781Subsequent heating modifying organic coating composition
ExaminersPrimary: Nguyen, Tan T.
Assistant: Whipple, Matthew
International ClassH01L 021/312
AbstractA low dielectric constant (k) polymer is used for an interlayer dielectric (28) of a semiconductor device (20). Unlike prior art low k polymer materials, a photoresist layer can be deposted directly on interlayer dielectric (28) due to the presence of an in-situ glass layer (32) formed within the interlayer dielectric. Glass layer (32) is formed by silylating the upper surface of the polymer material and then oxygenating the upper surface, for example in a plasma environment in an oxygen atmosphere. Silylation can occur, for example, by implantation, vapor phase diffusion, or liquid phase diffusion of silicon into the upper surface of the polymer. The silylation and oxygenation processes are performed at low temperature and are thus compatible with use of organic polymer films.