Apparatus for the localized reduction of the lifetime of charge carriers, particularly in integrated electronic devices
Patent 5900652 Issued on May 4, 1999. Estimated Expiration Date: 
July 25, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 25, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and structure for controllng carrier lifetime in semiconductor devices Method for preventing latchup in CMOS devices Method of making silicon material with enhanced surface mobility by hydrogen ion implantation Patent #: 5198371 InventorsAssigneeApplicationNo. 507048 filed on 07/25/1995US Classes:257/135, Vertical (i.e., where the source is located above the drain or vice versa)257/148, Having impurity doping for gain reduction257/156, Having deep level dopants or recombination centers257/394, With means to prevent parasitic conduction channels257/547, With structural means to control parasitic transistor action or leakage current257/590, With means to reduce minority carrier lifetime (e.g., region of deep level dopant or region of crystal damage)257/E21.137, To control carrier lifetime, i.e., deep level dopant (EPO)257/E21.319, Using cavities formed by inert gas ion implantation, e.g., hydrogen, noble gas (EPO)257/E21.335, In Group IV semiconductor (EPO)257/E21.383, Vertical insulated gate bipolar transistor (EPO)257/E21.418, Vertical power DMOS transistor (EPO)257/E21.608, Bipolar technology (EPO)257/E29.107, Imperfections within semiconductor body (EPO)257/E29.257Having vertical bulk current component or current vertically following trench gate (e.g., vertical power DMOS transistor) (EPO)ExaminersPrimary: Tran, Minh LoanAttorney, Agent or FirmForeign Patent References
International ClassH01L 029/74Foreign Application Priority Data1994-07-25 EPAbstractA method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrated device so that the ions form bubbles in the active regions. A further thermal treatment is performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, leaving cavities in the active regions.Other References
Field of SearchCombined with field effect transistorVertical (i.e., where the source is located above the drain or vice versa) Having impurity doping for gain reduction Having impurity doping for gain reduction Having deep level dopants or recombination centers Vertical channel or double diffused insulated gate field effect device provided with means to protect against excess voltage (e.g., gate protection diode) Plural sections connected in parallel (e.g., power MOSFET) With means to prevent parasitic conduction channels With structural means to control parasitic transistor action or leakage current With means to reduce minority carrier lifetime (e.g., region of deep level dopant or region of crystal damage) | |
