Lockout circuit and method for preventing metastability during the termination of a refresh mode
Circuit having a control array of memory cells and a current source and a method for generating a self-refresh timing signal
Non-volatile semiconductor memory device incorporating data latch and address counter for page mode programming
Write pass through circuit
DRAM having multiple column address strobe operation Patent #: 5703813
ApplicationNo. 918635 filed on 08/22/1997
US Classes:365/230.06, Particular decoder or driver circuit365/230.08Including particular address buffer or latch circuit arrangement
ExaminersPrimary: Nelms, David C.
Assistant: Lam, David
Attorney, Agent or Firm
International ClassG11C 008/00
AbstractA memory is described which includes circuitry to modify the operation of a write driver circuit in a memory device in response to a command to close an accessed memory location. The memory includes a write driver circuit for actively driving a data signal during a portion of a write operation. The write driver operation is selectively modified to simultaneously operate with a sense amplifier to complete a write operation prior to closing an accessed row of the array.