U.S. patents available from 1976 to present.
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Static memory cell having independent data holding voltage

Patent 5894433 Issued on April 13, 1999. Estimated Expiration Date: Icon_subject September 15, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Static type semiconductor memory device
Patent #: 4455627
Issued on: 06/19/1984
Inventor: Oritani

Static random access memory
Patent #: 4901284
Issued on: 02/13/1990
Inventor: Ochii, et al.

Internal low voltage transformation circuit of static random access memory
Patent #: 5046052
Issued on: 09/03/1991
Inventor: Miyaji, et al.

Static random access memory of an energy-saving type
Patent #: 5140557
Issued on: 08/18/1992
Inventor: Yoshida

Static random access memory resistant to soft error
Patent #: 5303190
Issued on: 04/12/1994
Inventor: Pelley, III

Static memory device
Patent #: 5309401
Issued on: 05/03/1994
Inventor: Suzuki, et al.

Static random access memory device with low power dissipation Patent #: 5646902
Issued on: 07/08/1997
Inventor: Park

Inventors

Assignee

Application

No. 929890 filed on 09/15/1997

US Classes:

365/154, Flip-flop (electrical)365/226, POWERING365/227Conservation of power

Examiners

Primary: Nguyen, Tan T.

Attorney, Agent or Firm

Foreign Patent References

  • 60-38796 JP. 02/21/1985
  • 2-108297 JP. 04/21/1990
  • 4-276386 JP. 10/21/1992

International Class

G11C 011/40

Foreign Application Priority Data

1995-06-02 JP

Abstract

A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Other References

  • K. Itoh, "VLSI Memory" (issued by Baifukan in Nov. 1994), pp. 310-328 and pp. 351-371
  • G. Kitsukawa et al, "A 1-Mbit BiCMOS DRAM Using Temperature-Comensation Circuit Techniques", IEEE Journal of Solid-State Circuits, vol. 24, No. 3, Jun. 1989, pp. 597-602
  • Y. Nakagome et al, "An Experimental 1.5-V 64Mb DRAM", IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 465-471
  • M. Horiguchi et al, "Switched-Source-Impedance CMOS Circuit For Low Standby Subthreshold Current Giga-Scale LSI's", IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993, pp. 1131-1135
  • K. Sawada et al, "An On-Chip High-Voltage Generator Circuit for EEPROMs with a Power Supply Voltage below 2V", 1995 Symposium on VLSI Circuits Digest of Technical Papers, pp. 75-7
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