Patent ReferencesBridge circuit for interconnecting networks Generic high bandwidth adapter having data packet memory configured in three level hierarchy for temporary storage of variable length data packets IP bridge for parallel machines System for memory table cache reloads in a reduced number of cycles using a memory controller to set status bits in the main memory table Method and apparatus for routing for virtual networks Network packet switch using shared memory for repeating and bridging packets at media rate Internet protocol (IP) work group routing Processor and data memory for outputting and receiving data on different buses for storage in the same location Bridge/router architecture for high performance scalable networking Method for accessing memory by activating a programmable chip select signal Patent #: 5813041 InventorApplicationNo. 808021 filed on 02/28/1997US Classes:709/238COMPUTER-TO-COMPUTER DATA ROUTINGExaminersPrimary: Asta, Frank J.Assistant: Vu, Hung Attorney, Agent or FirmInternational ClassG06F 015/16AbstractA VLAN memory access system to provide VLAN address table look-ups with the ability to simultaneously do processor read cycles or processor write cycles to the same memory structure with anatomical accesses. The system encompasses the interaction between a memory look-up table that stores the slot allowed transition bit mask for a multi-slot hub based VLAN switch, a switch processor interface that is used to upgrade the memory access table by writing entries into the table or reading the table to verify its contents, and a look-up processor that uses the VLAN table to make forwarding decisions on the destination of a packet based on the value read from the VLAN memory look-up table. The VLAN table accesses must be arbitrated between the look-up processor, which has the highest priority, and read or write accesses from the switch processor. The look-up processor takes the VLAN ID field of a packet and uses this as the address of the slot allowed transmit bit mask to be applied to the destination slot bit mask. This logical AND function is used to determine the final bit mask of slots that will receive this packet.Other References
| |