Method and system in a data processing system for loading and storing vectors in a plurality of modes
March 23, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcessing unit for multiplying two mathematical quantities including at least one complex multiplier Vector processing Apparatus for out-of-order program execution Complex arithmetic vector processor for performing control function, scalar operation, and set-up of vector signal processing instruction Digital data processor for matrix-vector multiplication Architecture for block processing computer system Loop control mechanism for scientific processor Scientific processor to support a host processor referencing common memory Vector processor with vector data compression/expansion capability Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements Inventors
ApplicationNo. 368173 filed on 01/04/1995US Classes:712/2, Vector processor712/4, Distributing of vector data to vector registers712/17Application specificExaminersPrimary: Coleman, EricAttorney, Agent or FirmInternational ClassG06F 015/80AbstractA vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers. | |
