Semiconductor device and manufacturing method thereof
Patent 5886385 Issued on March 23, 1999. Estimated Expiration Date: 
August 20, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
August 20, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSOS p--n Junction device with a thick oxide wiring insulation layer MOS type field effect transistor formed on a semiconductor layer on an insulator substrate Insulated-gate transistor having narrow-bandgap-source Patent #: 5698869 InventorsAssigneeApplicationNo. 914752 filed on 08/20/1997US Classes:257/347, Single crystal semiconductor layer on insulating substrate (SOI)257/23, Current flow across well257/67, In combination with device formed in single crystal semiconductor material (e.g., stacked FETs)257/192, Field effect transistor257/194, Doping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT))257/E21.415, Monocrystalline silicon transistor on insulating substrate, e.g., quartz substrate (EPO)257/E29.147, For thin-film silicon (EPO)257/E29.277, Characterized by drain or source properties (EPO)257/E29.281For preventing kink or snapback effect (e.g., discharging minority carriers of channel region for preventing bipolar effect) (EPO)ExaminersPrimary: Brown, Peter R.Assistant: Duong, Hung Van Attorney, Agent or FirmForeign Patent References
International ClassesH01L 027/01H01L 029/78 Foreign Application Priority Data1996-08-22 JPAbstractA semiconductor device comprises: a first semiconductor layer 6 having a first conductivity formed on a substrate having a surface of an insulating material 4; a source region 16a and a drain region 16b, which are formed on the first semiconductor layer so as to be separated from each other and which have a second conductivity different from the first conductivity; a channel region 6 formed on the first semiconductor layer between the source region and the drain region; a gate electrode 10 formed on the channel region a gate sidewall 14 of an insulating material formed on a side of the gate electrode; and a second semiconductor layer 18 having the first conductivity formed on at least the source region. This semiconductor device can effectively suppress the floating-body effect with a simple structure.Other References
Field of SearchField effect transistorDoping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT)) In combination with device formed in single crystal semiconductor material (e.g., stacked FETs) Current flow across well Single crystal semiconductor layer on insulating substrate (SOI) | |
