Method for testing an integrated circuit with user definable trace function
December 9, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesModularized scan path for serially tested logic circuit Logic circuit having individually testable logic modules Hierarchical scan selection Data processing device with multiple on chip memory buses Series maxium/minimum function computing devices, systems and methods Enhanced test circuit Real time probe device for internals of signal processor Emulation devices, systems and methods utilizing state machines Method and apparatus for debugging reconfigurable emulation systems Processor condition sensing circuits, systems and methods InventorsAssigneeApplicationNo. 762487 filed on 12/09/1996US Classes:714/30Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path)ExaminersPrimary: Beausoliel, Robert W. Jr.Assistant: Elmore, Stephen C. Attorney, Agent or FirmForeign Patent References
International ClassG06F 011/00AbstractA method for testing a digital processor 11 in which a test port 1149 is used to transfer trace data from the digital processor to a test host processor 1101 under control of a user definable program which executes in response to predetermined events on the digital processor. Trace data is gathered while an application program loaded in program memory 61 is executed by the digital processor. Trace data is temporarily stored in a trace region 99 of data memory 25 by user definable code which is executed in a background manner by the digital processor in response to trigger events. The trigger events are also enabled by user definable code which enables various portions of analysis hardware 1217. Trace data is transferred from the digital processor to the test host processor through test port 1149 by sending a notification signal to the test host processor by means of message passing register 1216. The digital processor then monitors the message passing register for a handshake signal from the test host processor. When a handshake signal is received, trace data is written into the message passing register by user definable code in a background manner and transferred to the test host processor.Other References
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