Latch type sense amplifier having a negative feedback device
Patent 5883846 Issued on March 16, 1999. Estimated Expiration Date: 
July 28, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 28, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMemory device comprising thin film memory transistors High-speed sense amplifier having feedback loop Sense amplifier with pull-up circuit for accelerated latching of logic level output data Clocked sense amplifier with positive source feedback Patent #: 5615161 InventorAssigneeApplicationNo. 901627 filed on 07/28/1997US Classes:365/207, Differential sensing365/189.05, Having particular data buffer or latch365/205Flip-flop used for sensingExaminersPrimary: Nelms, David C.Assistant: Lam, David Attorney, Agent or FirmInternational ClassG11C 007/02Foreign Application Priority Data1996-07-29 KRAbstractA latch type sense amplifier having negative feedback means for use in a memory device includes a first switching unit which is turned on/off by an enable signal and initializes a system operation at a turn-on operation; a second switching unit which is turned on/off according to the voltage state of the data on two data lines at the turn-on operation of the first switching unit and performs a system initial operation; a third switching unit which is turned on by a precharge signal and initializes two output signals; a latch unit for latching the data input via the second switching unit according to the operation of the third switching unit and outputting the latched data to two data output units; and a feedback switching unit which is connected to the data output units of the latch unit and the data lines, is turned on/off according to the voltage state of the other data output unit and pulls-up the voltage difference of the bit line connected to corresponding data line by the voltage on corresponding data output terminal at an on operation.Other References
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