Semiconductor device and process and apparatus of fabricating the same
Patent 5880500 Issued on March 9, 1999. Estimated Expiration Date: 
July 3, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 3, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSubmicron lightly doped field effect transistors Self-aligned overlap MOSFET and method of fabrication Patent #: 5091763 InventorsApplicationNo. 675595 filed on 07/03/1996US Classes:257/336, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/344, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/382, With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide)257/E21.035, Characterized by their composition, e.g., multilayer masks, materials (EPO)257/E21.191, Insulator formed on silicon semiconductor body (EPO)257/E21.345, Characterized by the angle between the ion beam and the crystal planes or the main crystal surface (EPO)257/E21.435, Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)257/E21.438, Using self-aligned silicidation, i.e., salicide (EPO)257/E21.633, With particular manufacturing method of channel, e.g., channel implants, halo or pocket implants, or channel materials (EPO)257/E27.067, Including both N- and P- wells in the substrate, e.g. twin-tub (EPO)257/E29.063, With inactive supplementary region (e.g., for preventing punch-through, improving capacity effect or leakage current) (EPO)257/E29.266With lightly doped drain or source extension (EPO)ExaminersPrimary: Fahmy, WaelAttorney, Agent or FirmInternational ClassesH01L 029/76H01L 029/94 H01L 031/062 Foreign Application Priority Data1995-07-05 JPAbstractA semiconductor device having a gate electrode on a Si-substrate through a gate oxide film; a first impurity diffusion region having a conductivity type reversed to a well which will form a part of source and drain regions in the two opposing sides of the gate electrode through gate electrode sidewall dielectric films; a second impurity diffusion region having the same conductivity type as the first impurity diffusion region beneath the gate electrode sidewall dielectric film, touching a channel region directly below the gate electrode and being shallower than the first impurity diffusion region; a titanium silicide film on the gate electrode and the surface of the Si-substrate of the first impurity diffusion region in the two opposing sides of the gate electrode sidewall dielectric film; and a third impurity diffusion region, formed in the first impurity diffusion region, having a higher concentration than the first impurity diffusion region and the same conductivity type as the first and second impurity diffusion region. The above semiconductor device is able to suppress the short-channel effects, and reduce the source-drain parasitic resistance and the source-drain junction leakage current while maintaining a small source-drain capacity.Other References
Field of SearchActive channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)With lightly doped portion of drain region adjacent channel (e.g., LDD structure) With lightly doped portion of drain region adjacent channel (e.g., LDD structure) With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide) Contact of refractory or platinum group metal (e.g., molybdenum, tungsten, or titanium) Including silicide Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device) | |
