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Silicon-germanium devices for CMOS formed by ion implantation and solid phase epitaxial regrowth

Patent 5879996 Issued on March 9, 1999. Estimated Expiration Date: Icon_subject September 18, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Methods of manufacturing a semiconductor device having a channel region spaced inside channel stoppers
Patent #: 4394181
Issued on: 07/19/1983
Inventor: Nicholas

Formation of shallow junction by implantation of dopant into partially crystalline disordered region
Patent #: 5145794
Issued on: 09/08/1992
Inventor: Kase, et al.

Method for recrystallization of preamorphized semiconductor surfaces zones
Patent #: 5254484
Issued on: 10/19/1993
Inventor: Hefner, et al.

Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon
Patent #: 5298435
Issued on: 03/29/1994
Inventor: Aronowitz, et al.

Method of providing lower contact resistance in MOS transistors
Patent #: 5312766
Issued on: 05/17/1994
Inventor: Aronowitz, et al.

Method for making silicon-germanium devices using germanium implantation Patent #: 5426069
Issued on: 06/20/1995
Inventor: Selvakumar, et al.

Inventor

Application

No. 717198 filed on 09/18/1996

US Classes:

438/289, Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.)257/E21.335, In Group IV semiconductor (EPO)257/E21.409, With an insulated gate (EPO)257/E29.056, With variation of composition of channel (EPO)438/299, Self-aligned438/528Providing nondopant ion (e.g., proton, etc.)

Examiners

Primary: Trinh, Michael

Attorney, Agent or Firm

Foreign Patent References

  • 4-34942 JP 02/13/1992

International Class

H01L 021/336

Abstract

A PMOS transistor is formed in a CMOS integrated circuit, having a Si1-x Gex /Si heterojunction between the channel region and the substrate. The method is applicable to large volume CMOS IC fabrication. Germanium is implanted into a silicon substrate, through a gate oxide layer. The substrate is then annealed in a low temperature furnace, to form Si1-x Gex in the channel region.

Other References

  • M. Berti, et al., "Composition and Structure of Si-Ge Layers Produced by Ion Implantation and Laser Melting", J. Mater. Res., vol. 6, No. 10, pp. 2120-2126, Oct. (1991)
  • M. Berti, et al., "Laser Induced Epitaxial Regrowth of Si1-x Gex /Si Layers Produced by Ge Ion Implantation", Appl. Surf. Sci. vol. 43, pp. 158-164, Jan. (1989)
  • B. T. Chilton, et al., "Solid Phase Epitaxial Regrowth of Strained Si1-x Gex /Si Strained-layer Structures Amorphized by Ion Implantation", Appl. Phys. Lett., vol. 54, No. 1, pp. 42-44, Jan. (1989)
  • Vandebroek, Bernard S. Myerson, et al., "SiGe-Channel Heterojunction p-MOSFET's", IEEE Trans. on Electron Devices, vol. 41, No. 1, pp. 90-100, (Jan. 1994)
  • D. C. Paine, et al., "The Growth of Strained Si1-x Gex Alloys on (100) Silicon Using Solid Phase Epitaxy", J. Mater Re., vol. 5, No. 5, pp. 1023-1031, May (1990)
  • R. People, et al., "Calculation of critical layer thickness versus Lattice Mismatch for Si1 -xGex /Si Strained-layer Heterostructures", Appl. Phys. Lett., Aug. (1985), pp. 322-324, Erraltum
  • G.A. Garcia et al, "High Quality CMOS in Thin (100nm) Silicon on Sapphire", IEEE Elect. Device Lett, vol. 9, No. 1, pp. 32-34, (Jan. 1988)
  • D. K. Nayak, K. L. Wang, et al., "High Performance GeSi Quantum-Well PMOS on SIMOX", Proc. Int. Electron Device Meeting, San Francisco, pp. 777-780, (Dec. 1992
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