Patent ReferencesMethods of manufacturing a semiconductor device having a channel region spaced inside channel stoppers Formation of shallow junction by implantation of dopant into partially crystalline disordered region Method for recrystallization of preamorphized semiconductor surfaces zones Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon Method of providing lower contact resistance in MOS transistors Method for making silicon-germanium devices using germanium implantation Patent #: 5426069 InventorApplicationNo. 717198 filed on 09/18/1996US Classes:438/289, Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.)257/E21.335, In Group IV semiconductor (EPO)257/E21.409, With an insulated gate (EPO)257/E29.056, With variation of composition of channel (EPO)438/299, Self-aligned438/528Providing nondopant ion (e.g., proton, etc.)ExaminersPrimary: Trinh, MichaelAttorney, Agent or FirmForeign Patent References
International ClassH01L 021/336AbstractA PMOS transistor is formed in a CMOS integrated circuit, having a Si1-x Gex /Si heterojunction between the channel region and the substrate. The method is applicable to large volume CMOS IC fabrication. Germanium is implanted into a silicon substrate, through a gate oxide layer. The substrate is then annealed in a low temperature furnace, to form Si1-x Gex in the channel region.Other References
Field of SearchDoping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.)After formation of source or drain regions and gate electrode Using channel conductivity dopant of opposite type as that of source and drain Self-aligned Source or drain doping Plural doping steps Plural doping steps Using same conductivity-type dopant Providing nondopant ion (e.g., proton, etc.) Inverted transistor structure | |