4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation
January 22, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor memory cell Non-volatile semiconductor memory device Erasable electrically programmable read only memory cell using trench edge tunnelling Tunnel injection controlling type semiconductor device controlled by static induction effect Non-volatile semiconductor memory device and method of the manufacture thereof Three-dimensional memory cell with integral select transistor Floating gate memory cell and device Dram cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof Dram with a vertical capacitor and transistor 5016067 InventorsApplicationNo. 787419 filed on 01/22/1997US Classes:257/315, With floating gate electrode257/318, Additional control electrode is doped region in semiconductor substrate257/E21.652, In combination with vertical transistor (EPO)257/E21.693, For vertical channel (EPO)257/E27.096, Vertical transistor (EPO)257/E27.103, Electrically programmable ROM (EPO)257/E29.129, Gate electrodes for transistors with floating gate (EPO)257/E29.304Charging by tunneling of carriers (e.g., Fowler-Nordheim tunneling) (EPO)ExaminersPrimary: Meier, Stephen D.Attorney, Agent or FirmForeign Patent References
International ClassH01L 029/788AbstractA densely packed array of vertical semiconductor devices and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, acting as a channel, formed between source and drain regions. The source regions are self-aligned and located below the pillars. The source regions of adjacent bitlines are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F2 to be maintained. The isolated sources allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. The source may be initially implanted. Alternatively, the source may be diffused below the pillars after forming thereof. In this case, the source diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.Other References
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