Method of forming a self-aligned silicide device
September 11, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of forming conductive interconnect structure Method for forming capacitor compatible with high dielectric constant materials having a low contact resistance layer Method of reliably manufacturing a semiconductor device having a titanium silicide nitride Method for forming TiN film and TiN film/thin TiSi2 film, and method for fabricating semiconductor element utilizing the same Method of forming a barrier and landing pad structure in an integrated circuit Method for forming a semiconductor device electrode which also serves as a diffusion barrier Patent #: 5668040 InventorsAssigneeApplicationNo. 927321 filed on 09/11/1997US Classes:438/592, Possessing plural conductive layers (e.g., polycide)257/413, Polysilicon laminated with silicide257/E21.199, Conductor comprising silicide layer formed by silicidation reaction of silicon with metal layer (EPO)257/E21.2, Conductor comprising metal or metallic silicide formed by deposition e.g., sputter deposition, i.e., without silicidation reaction (EPO)257/E21.438, Using self-aligned silicidation, i.e., salicide (EPO)257/E29.155, Multiple silicon layers257/E29.157, Including barrier layer between silicon and non-Si electrode438/296, Dielectric isolation formed by grooving and refilling with dielectric material438/653, At least one layer forms a diffusion barrier438/655, Silicide438/657Having electrically conductive polysilicon componentExaminersPrimary: Booth, Richard A.Attorney, Agent or FirmInternational ClassesH01L 021/320.5H01L 021/476.3 Foreign Application Priority Data1997-07-31 TWAbstractA method of forming self-aligned silicide devices which includes providing a silicon substrate having shallow trench isolation regions for defining a device area formed therein; then, forming sequentially a gate oxide layer, a polysilicon layer, a first titanium nitride layer, a titanium silicide layer, a second titanium nitride layer and a silicon nitride layer over the substrate. After a gate electrode is etched out from the above layers, a titanium layer is deposited over the device, and then a self-aligned titanium silicide layer is formed using a heating process. The use of a titanium silicide layer having protective top and bottom titanium nitride layers, compared with a single tungsten silicide layer in a conventional method, provides for a self-aligned silicide device having a rather low gate resistance; being free from narrow width effect of a titanium self-aligned silicide layer; is applicable to self-aligned contact window processes, and avoids the cross-diffusion of doped ions in the polysilicon layer of a dual gate electrode having a tungsten polycide layer.Field of SearchPossessing plural conductive layers (e.g., polycide)At least one layer forms a diffusion barrier Silicide Having electrically conductive polysilicon component Dielectric isolation formed by grooving and refilling with dielectric material Gate electrode of refractory material (e.g., polysilicon or a silicide of a refractory or platinum group metal) Polysilicon laminated with silicide At least one layer forms a diffusion barrier At least one layer of silicide or polycrystalline silicon Silicide of refractory or platinum group metal | |
