Method of optimizing a chip pattern on a semiconductor wafer
Patent 5874189 Issued on February 23, 1999. Estimated Expiration Date: October 10, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
A method is disclosed for optimizing a pattern of semiconductor chips, which includes a mask being aligned via a reference point on the mask and an alignment mark on the wafer. The relative spatial position of the alignment mark is determined by a procedure for optimizing quantities which determine the fabrication costs of a semiconductor chip, while the position of the semiconductor chips relative to each other remain fixed during the optimization.