Consolidation of commands in a buffered input/output device
BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
Method and apparatus for priority selection of commands
Memory control unit with selective execution of queued read and write requests
Information processor comprising a write buffer circuit containing an address buffer and a data buffer corresponding to each other
Read-write buffer for gathering write requests and resolving read conflicts based on a generated byte mask code
Memory subsystems having look-ahead instruction prefetch buffers and intelligent posted write buffers for increasing the throughput of digital computer systems
System for arbitrating access to memory with dynamic priority assignment
Methods and system for merging data during cache checking and write-back cycles for memory reads and writes
ApplicationNo. 570441 filed on 12/11/1995
US Classes:710/5, Input/Output command process710/20Concurrent Input/Output processing and data transfer
ExaminersPrimary: Lee, Thomas C.
Assistant: Ton, David
Attorney, Agent or Firm
International ClassG06F 009/312
AbstractA computer system is disclosed which has a plurality of masters, such as a processor, a cache memory or an I/O device controller. Read response time from the main memory is minimized by a read-from-write scheme which gives priority to read commands. If a read command is to access data with the same address of a previously issued but pending write command in the buffer of a memory controller, then the read and write commands are combined and the read/write command is given priority over each other pending read or write command. To further reduce mean read response time, the data to be written to the main memory is transferred directly from the buffer to the master which issued the read command contemporaneously with the execution of the write command on the main memory.