Patent ReferencesThermal ink jet printhead with self-passivating elements Thermal ink jet printhead fabricating process Liquid jet recording head unit, method of making same and liquid jet recording apparatus incorporating same Thermal inkjet printhead having driver circuitry thereon and method for making the same Thermal ink-jet printhead method for generating homogeneous nucleation Method of fabricating ink jet printheads Control knob assembly for a cooking appliance Fabrication of ink fill slots in thermal ink-jet printheads utilizing chemical micromachining Method of producing a resistor in an integrated circuit Liquid jet recording head fabrication method InventorAssigneeApplicationNo. 947829 filed on 10/08/1997US Classes:347/59, Integrated347/62Resistor specificsExaminersPrimary: Hartary, Joseph W.Attorney, Agent or FirmForeign Patent References
International ClassB41J 002/05AbstractThe present invention provides a structure and a method of manufacturing a resistor in a semiconductor device and especially for a resistor in an ink jet print head. The method begins by providing a substrate 10 having a field oxide region 20 surrounding an active area. The field oxide region 20 has an ink well region 52. Also a transistor is provided in the active area. The transistor comprises a source 12, drain 14 and gate electrode 16 18 19. A dielectric layer 24 is formed over the field oxide region 20 and the transistor 12 14 16 18. The dielectric layer 24 has contact openings over the source 12 and drain 14. A resistive layer 26 27 is formed over the dielectric layer 24 and contacting the source 12 and drain 14. The resistive layer 26 27 is preferably comprised of two layers of: a Titanium layer 26 under a titanium nitride 27 or a titanium layer 26 under a tungsten nitride layer 27. A first metal layer 28 is formed over the resistive layer. The metal layer 28 is patterned forming an first opening 29 over a portion of the resistive layer 28 over the ink well region 52. The resistive layer and first metal layer are patterned forming a second opening 31 over the gate electrode 16 18 and forming the resistive layer and first metal layer into an interconnect layer. A passivation layer 30 is then formed over the first metal layer 28, the resistive layer 26 27 in the ink well region 52, and the gate electrode 16 18. | |