U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

System and method for creating and validating structural description of electronic system from higher-level and behavior-oriented description

Patent 5867399 Issued on February 2, 1999. Estimated Expiration Date: Icon_subject April 21, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

T940008

T940020

Method of diagnosing errors off-line in pipe specification files of a computer-aided graphics system
Patent #: 4353117
Issued on: 10/05/1982
Inventor: Spellmann

Processor for simulating digital structures
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Issued on: 05/06/1986
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Patent #: 4675832
Issued on: 06/23/1987
Inventor: Robinson ,   et al.

Hardware logic simulator
Patent #: 4697241
Issued on: 09/29/1987
Inventor: Lavi

Logic Synthesizer
Patent #: 4703435
Issued on: 10/27/1987
Inventor: Darringer ,   et al.

Design support method and apparatus therefor
Patent #: 4789944
Issued on: 12/06/1988
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Method of updating layout of circuit element
Patent #: 4805113
Issued on: 02/14/1989
Inventor: Ishii ,   et al.

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Inventors

Assignee

Application

No. 847930 filed on 04/21/1997

US Classes:

716/18, Logical circuit synthesizer716/2, Optimization (e.g., redundancy, compaction)716/6, Timing analysis (e.g., delay time, path delay, latch timing)716/12Routing (e.g., routing map, netlisting)

Examiners

Primary: Trans, Vincent N.

Foreign Patent References

  • 0 319 232 A2 EP. 06/13/1989
  • 0 463 301 A2 EP 01/13/1992
  • 0 473 960 A2 EP. 03/13/1992

International Class

B06F 017/50

Abstract

A system for interactive design and simulation of an electronic circuit allowing a user to design a circuit by graphical entry and to view full or partial simulation and design results simultaneously, on a single display window. The user is able to define the form of a display of speed, delay, loading, symbols, simulation input and/or output values on each node and any path of the design. Simulation may be user-defined or other process time. The user is further able to view any information relevant to any object in the design at any level of design abstraction, and is able to view multiple levels of design abstraction simultaneously and to display information common to the various representations.

Other References

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