Method and apparatus for routing a clock tree in an integrated circuit package
Patent 5866924 Issued on February 2, 1999. Estimated Expiration Date: 
October 10, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 10, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDistributed clock tree scheme in semiconductor packages Clock supply circuit layout in a circuit area Clock distribution and control in an integrated circuit Hierarchical clock distribution system and method Patent #: 5570045 InventorApplicationNo. 948409 filed on 10/10/1997US Classes:257/208, With particular signal path connections257/211, Multi-level metallization257/776, Cross-over arrangement, component or structure257/777Chip mounted on chipExaminersPrimary: Martin-Wallace, ValenciaAssistant: Hardy, David B. Attorney, Agent or FirmInternational ClassH01L 023/528AbstractA method and apparatus for routing a clock tree in an integrated circuit device. Prior art clock trees were routed entirely on an integrated circuit device, thereby increasing the size, complexity, and cost of the integrated circuit. The present invention provides for a design wherein the clock tree is partitioned into one or more local clock trees and a global clock tree. A local clock tree is defined as a cluster of clock sinks coupled together. The global clock tree is defined as the interconnect between the local clock tree and the clock source. The local clock tree is routed on a device layer of the integrated circuit. The global clock tree is routed on a package layer of the integrated circuit package. The package layer is coupled to the device layer through a plurality of contacts.Field of SearchWith particular chip input/output meansWith particular power supply distribution means With particular signal path connections With wiring channel area Multi-level metallization For plural devices With discrete components Of specified configuration Cross-over arrangement, component or structure Chip mounted on chip Flip chip Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit) | |
