Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization
Dual cache for independent prefetch and execution units
Prioritized secondary use of a cache with simultaneous access
Methods and apparatus for providing multiple pending operations in a cache consistent multiple processor computer system
Digital computer system with cache controller coordinating both vector and scalar operations
Architecture of transfer processor
Synchronized data transmission between elements of a processing system
System and method for handling load and/or store operations in a superscalar microprocessor Patent #: 5659782
ApplicationNo. 751149 filed on 11/15/1996
US Classes:711/118, Caching711/130Shared cache
ExaminersPrimary: Swann, Tod R.
Assistant: Lee, Felix B.
Attorney, Agent or Firm
International ClassG06F 013/00
AbstractA cache control unit and a method of controlling a cache. The cache is coupled to a cache accessing device. A first cache request is received from the device. A request identification information is assigned to the first cache request and provided to the requesting device. The first cache request may begin to be processed. A second cache request is received from the cache accessing device. The second cache request is assigned to the first cache request and provided to the requesting device. The first and second cache requests are finally fully serviced.