Integrated dual layer emitter mask and emitter trench for BiCMOS processes

Patent 5856697 Issued on January 5, 1999. Estimated Expiration Date:

July 14, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Method for making a base etched transistor integrated circuit
Patent #: 4435898
Issued on: 03/13/1984
Inventor: Gaur , et al.

Method of producing a bipolar CMOS device
Patent #: 5132234
Issued on: 07/21/1992
Inventor: Kim, et al.

Reverse self-aligned BiMOS transistor integrated circuit
Patent #: 5175606
Issued on: 12/29/1992
Inventor: Tsai, et al.

BICMOS device and manufacturing method thereof
Patent #: 5192992
Issued on: 03/09/1993
Inventor: Kim, et al.

Method for manufacturing BICMOS devices
Patent #: 5196356
Issued on: 03/23/1993
Inventor: Won, et al.

Method for making a shallow junction bipolar transistor and transistor formed thereby
Patent #: 5198372
Issued on: 03/30/1993
Inventor: Verret

Method of forming bipolar transistor having substrate to polysilicon extrinsic base contact
Patent #: 5204277
Issued on: 04/20/1993
Inventor: Somero, et al.

Method for forming a grown bipolar electrode contact using a sidewall seed
Patent #: 5213989
Issued on: 05/25/1993
Inventor: Fitch, et al.

Monolithic IC formed of a CCD, CMOS and a bipolar element Patent #: 5319235
Issued on: 06/07/1994
Inventor: Kihara, et al.

Inventors

Application

No. 895270 filed on 07/14/1997

US Classes:

257/378, Combined with bipolar transistor257/370, Combined with bipolar transistor257/E21.696Bipolar and MOS technologies (EPO)

Examiners

Primary: Meier, Stephen D.

Attorney, Agent or Firm

Blakely, Sokoloff, Taylor & Zafman LLP

Foreign Patent References

0033495 EP. 01/11/1981

International Classes

H01L 029/76
H01L 029/94
H01L 031/062
H01L 031/113

Abstract

A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.