Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit
November 19, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcess for improved planarization of the passivation layers for semiconductor devices Semiconductor planarization process for submicron devices Charge neutralization using silicon-enriched oxide layer Sog with moisture resistant protective capping layer Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device Method for depositing an insulating interlayer in a semiconductor metallurgy system Method for forming metal via One-transistor one-capacitor memory cell structure for DRAMs Aspect ratio independent coating for semiconductor planarization using SOG Multi-level interconnection CMOS devices with SOG InventorsApplicationNo. 753009 filed on 11/19/1996US Classes:257/347, Single crystal semiconductor layer on insulating substrate (SOI)257/374, Dielectric isolation means (e.g., dielectric layer in vertical grooves)257/397, In vertical-walled groove257/510, Dielectric in groove257/518, With polycrystalline connecting region (e.g., polysilicon base contact)257/908, DRAM CONFIGURATION WITH TRANSISTORS AND CAPACITORS OF PAIRS OF CELLS ALONG A STRAIGHT LINE BETWEEN ADJACENT BIT LINES257/E21.576, Characterized by formation and post treatment of dielectrics, e.g., planarizing (EPO)257/E23.144, Capacitive arrangements or effects of, or between wiring layers (EPO)257/E23.167Insulating materials (EPO)ExaminersPrimary: Martin-Wallace, ValenciaAttorney, Agent or FirmForeign Patent References
International ClassH01L 029/00AbstractA structure and method of maximizing the volume of low dielectric constant material between adjacent traces of a conductive interconnect structure. A semiconductor structure includes a semiconductor substrate, a first insulating layer located over the semiconductor substrate, a conductive interconnect layer having a plurality of conductive traces located over the first insulating layer, and a patterned insulating layer located over the patterned interconnect layer. One or more trenches are formed in the upper surface of the first insulating layer. These trenches, which do not extend completely through the first insulating layer, are located between adjacent traces of the interconnect layer. A dielectric material having a low dielectric constant is located in these trenches, and between adjacent traces of the patterned interconnect layer. The trenches advantageously maximize the volume of low dielectric constant material which is located between the traces.Field of SearchThree or more insulating layersAt least one layer of glass Planarized to top of insulating layer Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit) Single crystal semiconductor layer on insulating substrate (SOI) Dielectric isolation means (e.g., dielectric layer in vertical grooves) In vertical-walled groove Dielectric in groove Vertical walled groove With polycrystalline connecting region (e.g., polysilicon base contact) DRAM CONFIGURATION WITH TRANSISTORS AND CAPACITORS OF PAIRS OF CELLS ALONG A STRAIGHT LINE BETWEEN ADJACENT BIT LINES | |
