Method of forming dielectric thin films on silicon by low energy ion beam bombardment
Method of fabricating a polycidegate employing nitrogen/oxygen implantation
Polycrystalline silicon device electrode and method
Method for achieving an ultra-reliable thin oxide using a nitrogen anneal
Method for achieving a high quality thin oxide using a sacrificial oxide anneal
Low temperature plasma oxidation process
Method of manufacturing a semiconductor device having a polycide structure
Multilayer polysilicon gate self-align process for VLSI CMOS device
Method for fabricating hybrid oxides for thinner gate devices
Method of making MOS transistor having improved oxynitride dielectric
ApplicationNo. 784195 filed on 01/15/1997
US Classes:438/301, Source or drain doping257/E21.193, On single crystalline silicon (EPO)257/E21.241, Post-treatment (EPO)257/E21.251, By chemical means (EPO)438/770Oxidation
ExaminersPrimary: Booth, Richard A.
Attorney, Agent or Firm
International ClassesH01L 021/31
AbstractA method for fabrication a gate dielectric in which an initial dielectric layer comprising a sacrificial portion and a permanent portion is formed on the semiconductor substrate. Thereafter the sacrificial portion is controllably removed with an etchback process. The gate dielectric is preferably comprised of oxynitride to reduce boron penetration from the conductive gate into the transistor channel region and the gate dielectric has a final thickness less than approximately 30 angstroms. The method includes providing a semiconductor substrate having channel region that is laterally displaced between a pair of source/drain regions. An upper surface of said semiconductor substrate is then cleaned and the semiconductor substrate is loaded into an oxidation chamber containing a first ambient maintained at a first temperature for a first duration to grow an initial dielectric layer over the channel region of said semiconductor substrate. The first ambient includes a nitrogen bearing species, and the initial dielectric layer includes a sacrificial portion formed over a permanent portion. A gate dielectric is then formed by etching back the initial dielectric layer at a first etch rate to remove said sacrificial portion of the gate dielectric over the channel region. The gate dielectric is then annealed in an inert ambient maintained at an anneal temperature for an anneal duration. Thereafter, a conductive gate structure is formed on the gate dielectric aligned over the channel region of the semiconductor substrate and a pair of s/d structures are formed in a pair of s/d regions respectively of said semiconductor substrate. The pair of s/d regions are laterally displaced on either side of the channel region of the semiconductor substrate.