Programmable multiplexing input/output port
January 8, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesPLA With time division multiplex feature for improved density Optoelectronic integrated circuit multiplex Time-division-multiplexed data transmission system Interleaved time-division multiplexor with phase-compensated frequency doublers Input/output macrocell for programmable logic device Programmable logic cell and array Asynchronous glitchless digital MUX I/O cell for programmable logic device providing latched, unlatched, and fast inputs Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements Peripheral port with volatile and non-volatile configuration InventorsAssigneeApplicationNo. 780527 filed on 01/08/1997US Classes:326/39, Array (e.g., PLA, PAL, PLD, etc.)326/41, Significant integrated structure, layout, or layout interconnections326/93CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATESExaminersPrimary: Santamauro, JonAssistant: Roseen, Richard International ClassesH03K 007/38H03K 019/00 AbstractA programmable logic circuit includes a programmable logic array which generates a plurality of output signals for output from a single port on the programmable logic circuit, and which processes a plurality of input signals received from a single port on the programmable logic circuit. The programmable logic circuit also includes multiplexing means for receiving the plurality of output signals generated by the programmable logic array and for multiplexing the plurality of output signals. An output port outputs, from the programmable logic circuit, the multiplexed plurality of output signals generated by the programmable logic array. An input port receives a multiplexed plurality of input signals, and a demultiplexing means demultiplexes the multiplexed plurality of input signals and configurably communicates the demultiplexed plurality of input signals to the programmable logic array. This demultiplexing means and the multiplexing means are each operable at a clock speed which is different from a clock speed of the programmable logic array.Other References
Field of SearchHaving details of setting or programming of interconnections or logic functionsArray (e.g., PLA, PAL, PLD, etc.) With flip-flop or sequential device Significant integrated structure, layout, or layout interconnections Sequential (i.e., finite state machine) or with flip-flop Multiplexing combined with demultiplexing Multiplexing plural input channels to a common output channel Demultiplexing single input channel to plural output channels Converging with plural inputs and single output Diverging with single input and plural outputs | |
