Circuit and method for scheduling instructions by predicting future availability of resources required for execution
Patent 5842036 Issued on November 24, 1998. Estimated Expiration Date: 
October 20, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 20, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesCentral processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution Apparatus for pipeline streamlining where resources are immediate or certainly retired Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path Patent #: 5604878 InventorsApplicationNo. 954444 filed on 10/20/1997US Classes:712/23, Superscalar712/216, DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION712/217, Scoreboarding, reservation station, or aliasing712/218Commitment control or register bypassExaminersPrimary: Donaghue, Larry D.Attorney, Agent or FirmForeign Patent References
International ClassG06F 009/38AbstractAn out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution. | |
