Patent References 3874936 Semiconductor fabrication method for improved device yield by minimizing pipes between common conductivity type regions Semiconductor device Patent #: 4956693 InventorsAssigneeApplicationNo. 160704 filed on 12/01/1993US Classes:438/471, GETTERING OF SUBSTRATE257/E21.319, Using cavities formed by inert gas ion implantation, e.g., hydrogen, noble gas (EPO)257/E21.335, In Group IV semiconductor (EPO)438/473By implanting or irradiatingExaminersPrimary: Chaudhari, ChandraAttorney, Agent or FirmInternational ClassH01L 021/306AbstractImpurity gettering in silicon wafers is achieved by a new process consisting of helium ion implantation followed by annealing. This treatment creates cavities whose internal surfaces are highly chemically reactive due to the presence of numerous silicon dangling bonds. For two representative transition-metal impurities, copper and nickel, the binding energies at cavities were demonstrated to be larger than the binding energies in precipitates of metal silicide, which constitutes the basis of most current impurity gettering. As a result the residual concentration of such impurities after cavity gettering is smaller by several orders of magnitude than after precipitation gettering. Additionally, cavity gettering is effective regardless of the starting impurity concentration in the wafer, whereas precipitation gettering ceases when the impurity concentration reaches a characteristic solubility determined by the equilibrium phase diagram of the silicon-metal system. The strong cavity gettering was shown to induce dissolution of metal-silicide particles from the opposite side of a wafer. | |