High performance self modifying on-the-fly alterable logic FPGA, architecture and method
August 21, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProgrammable integrated circuit micro-sequencer device Configuration control circuit for programmable logic devices Dynamic control of configurable logic Programmable logic device which stores more than one configuration and means for switching configurations Hierarchically connectable configurable cellular array Non-disruptive, randomly addressable memory system Shadow DRAM for programmable logic devices System and method for dynamically reconfiguring a programmable gate array Patent #: 5646544 InventorApplicationNo. 700966 filed on 08/21/1996US Classes:326/38, Having details of setting or programming of interconnections or logic functions326/39, Array (e.g., PLA, PAL, PLD, etc.)326/40With flip-flop or sequential deviceExaminersPrimary: Tokar, MichaelAssistant: Roseen, Richard Attorney, Agent or FirmForeign Patent References
International ClassesH03K 019/173H03K 007/38 AbstractA technique for configuring arrays of programmable logic cells, including those associated with FPGA devices, through a novel DRAM-based configuration control structure that enables not only "on-the-fly" alterable chip and similar device reconfigurations, but, where desired, self-modifying reconfigurations for differing functionalities of the devices, eliminating current serious reconfigurability limitations and related problems, while providing significantly enhanced system performance at low cost. A large amount of memory is available internal to the FPGA and is accessed with a small number of pins such that the reconfiguration time is, for example, four orders of magnitude faster than the traditional approaches and at notably low cost. | |
