Hardware instruction scheduler for short execution unit latencies
March 7, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesInstruction issuing mechanism for processors with multiple functional units Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies Parallel processor system for processing natural concurrencies and method therefor Method for optimizing instruction scheduling for a processor having multiple functional resources Parallel processor instruction dispatch apparatus with interrupt handler Apparatus for controlling execution of a program in a computing device Multiport memory bypass under software control Semiconductor floor plan for a register renaming circuit Method and apparatus for grouping multiple instructions, issuing grouped instructions simultaneously, and executing grouped instructions in a pipelined processor Computer with instructions that use an address field to select among multiple condition code registers Patent #: 5517628 InventorsApplicationNo. 612130 filed on 03/07/1996US Classes:712/215, Simultaneous issuance of multiple instructions712/23, Superscalar712/214, INSTRUCTION ISSUING712/216, DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION712/217Scoreboarding, reservation station, or aliasingExaminersPrimary: Bowler, Alyssa H.Assistant: Davis, Walter D. International ClassG06F 009/06AbstractA pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.Other References
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