Apparatus and method for parallel computation

Patent 5832272 Issued on November 3, 1998. Estimated Expiration Date:

October 27, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Compiling method for determining programs to be executed parallelly by respective processors in a parallel computer which transfer data with a data identifier to other processors
Patent #: 5088034
Issued on: 02/11/1992
Inventor: Ihara, et al.

Method of processing a program by parallel processing, and a processing unit thereof
Patent #: 5410696
Issued on: 04/25/1995
Inventor: Seki, et al.

Apparatus for detecting possibility of parallel processing and method thereof and a program translation apparatus utilized therein
Patent #: 5450554
Issued on: 09/12/1995
Inventor: Zaiki

Program parallelizing apparatus capable of optimizing processing time
Patent #: 5452461
Issued on: 09/19/1995
Inventor: Umekita, et al.

Device and method for parallelizing compilation optimizing data transmission Patent #: 5634059
Issued on: 05/27/1997
Inventor: Zaiki

Inventor

Kalantery, Nasser

Assignee

University of Westminister

Application

No. 525630 filed on 10/27/1995

US Classes:

717/149, For a parallel or multiprocessor system717/154Including analysis of program

Examiners

Primary: Voeltz, Emanuel T.
Assistant: Chavis, John Q.

Attorney, Agent or Firm

Cesari and McKenna, LLP

Foreign Patent References

2 227 108 GB. 07/12/1990
88/02514 WO. 04/12/1988

International Class

G06F 009/40

Foreign Application Priority Data

1993-03-15 GB

Abstract

Data processing apparatus for the execution of a sequential program, comprising at least one memory and a plurality of parallel processors all connected for mutual transfer of messages under the control of a control system; in which the processors are programmed each with part of the sequential program, those steps of each part, which would access or modify a data variable, being serially labeled in accordance with the intended sequence of the whole sequential program; in which the control system is arranged so as to label every message intended to access or modify the memory with a label corresponding to the serial label of the program step from which the message is derived; and in which the control system is arranged, for the or each memory, to allow memory-accessing and modifying operations only in the sequential order of the serial labels on the messages.

Other References

IEICE Transations, vol. E 74, No. 10, Oct. 1991, Tokyo, JP, pp. 3105-3114, XPOOO279295, Hironori Kasahara et al., A Fortran Parallelizing Compilation Scheme for Oscar Using Dependence Graph Analysis
Computer Architecture News, vol. 17, No. 3, Jun. 1989, New York, U.S., pp. 416-423, XP000035328, Hong-Men Su et al., on Data Synchronization for Multiprocessors
The 15th Annual International Symposium on Computer Architecture, 30, May 1988, Honolulu, Hawaii, pp. 393-400, Andr Seznec et al., Synchronizing Processors Through Memory, et