Patent ReferencesI/O Adapter with direct memory access to I/O control information Internal communication arrangement for a multiprocessor system Automatic update of topology in a hybrid network Input/output control technique utilizing multilevel memory structure for processor and I/O communication Buffer system for input/output portion of digital data processing system Multipurpose digital IC for communication and control network Building-block architecture of a multi-node circuit-and packet-switching system Multi-nodal communication network with coordinated responsibility for global functions by the nodes Routing system to interconnect local area networks High-speed mesh connected local area network Inventors
ApplicationNo. 675663 filed on 07/03/1996US Classes:709/200, MISCELLANEOUS709/232, Computer-to-computer data transfer regulating709/233, Transfer speed regulating709/235, Congestion avoiding710/57Fullness indicationExaminersPrimary: Swann, Tod R.Assistant: Tzeng, Fred F. Attorney, Agent or FirmForeign Patent References
International ClassG06F 013/00AbstractA communication technique for high volume connectionless-protocol, backbone communication links in distributed processing systems provides for control of latency and reliability of messages transmitted. The system provides for transmit list and receive list processes in the processors on the link. On the transmit side, a high priority command list and a normal priority command list are provided. In the message passing process, the command transmit function transmits commands across the backplane according to a queue priority rule that allows for control of transmit latency. Messages that require low latency are written into the high priority transmit list, while a majority of messages are written into the high throughput or normal priority transmit list. A receive filtering process in the receiving processor includes dispatch logic which dispatches messages either to a high priority receive list or a normal priority receive list. The filtering function also acts to drop messages received according to the amount of available buffer space in the receiving processor, as measured against watermarks based on reliability tags in message headers. The messages received are routed to either the high priority receive list or a normal priority receive list based on another control bit in the message headers. The receiving processor processes the messages in the receive queues according to a priority rule that allows for control of the latency between receipt of a message, and actual processing of the message by the receiving processor.Other References
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