U.S. patents available from 1976 to present.
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High throughput message passing process using latency and reliability classes

Patent 5828835 Issued on October 27, 1998. Estimated Expiration Date: Icon_subject July 3, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

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Inventors

Application

No. 675663 filed on 07/03/1996

US Classes:

709/200, MISCELLANEOUS709/232, Computer-to-computer data transfer regulating709/233, Transfer speed regulating709/235, Congestion avoiding710/57Fullness indication

Examiners

Primary: Swann, Tod R.
Assistant: Tzeng, Fred F.

Attorney, Agent or Firm

Foreign Patent References

  • WO 94/08415 WO. 04/13/1994

International Class

G06F 013/00

Abstract

A communication technique for high volume connectionless-protocol, backbone communication links in distributed processing systems provides for control of latency and reliability of messages transmitted. The system provides for transmit list and receive list processes in the processors on the link. On the transmit side, a high priority command list and a normal priority command list are provided. In the message passing process, the command transmit function transmits commands across the backplane according to a queue priority rule that allows for control of transmit latency. Messages that require low latency are written into the high priority transmit list, while a majority of messages are written into the high throughput or normal priority transmit list. A receive filtering process in the receiving processor includes dispatch logic which dispatches messages either to a high priority receive list or a normal priority receive list. The filtering function also acts to drop messages received according to the amount of available buffer space in the receiving processor, as measured against watermarks based on reliability tags in message headers. The messages received are routed to either the high priority receive list or a normal priority receive list based on another control bit in the message headers. The receiving processor processes the messages in the receive queues according to a priority rule that allows for control of the latency between receipt of a message, and actual processing of the message by the receiving processor.

Other References

  • Choi, et al., "Integrating Networks and Memory Hierarchies in a Multicomputer Node Architecture," IEEE, pp. 10-17, (1994
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