U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Semiconductor memory device having internal voltage booster circuit coupled to bit line charging/equalizing circuit

Patent 5828611 Issued on October 27, 1998. Estimated Expiration Date: Icon_subject May 19, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Sensing circuit for semiconductor memory with limited bitline voltage swing
Patent #: 5257232
Issued on: 10/26/1993
Inventor: Dhong, et al.

Semiconductor memory device provided with a word-line driver circuit using boosted voltage-source divided decoding
Patent #: 5361237
Issued on: 11/01/1994
Inventor: Chishiki

Dynamic control of configurable logic
Patent #: 5375086
Issued on: 12/20/1994
Inventor: Wahlstrom

Semiconductor device using boosted signal Patent #: 5412604
Issued on: 05/02/1995
Inventor: Fukuda, et al.

Inventors

Application

No. 859225 filed on 05/19/1997

US Classes:

365/203, Precharge365/189.07, Including signal comparison365/189.09, Including reference or bias voltage generator365/189.11, Including level shift or pull-up circuit365/226, POWERING365/228, Data preservation365/230.06Particular decoder or driver circuit

Examiners

Primary: Nelms, David C.
Assistant: Tran, Andrew Q.

Attorney, Agent or Firm

Foreign Patent References

  • 0 092 809 EP. 11/13/1983
  • 0 535 325 EP. 04/13/1993
  • 2 118 795 GB. 11/13/1983

International Class

G11C 007/00

Foreign Application Priority Data

1993-09-10 JP

Abstract

An equalizing circuit is connected between a pair of bit lines. The equalizing circuit is made up of three MOS transistors and an equalization control signal is supplied to the gates of the MOS transistors. A sense amplifier circuit is connected to the bit lines. The sense amplifier circuit amplifies the potential difference occurring between the bit lines, for the detection of data. The equalization control signal is output from a level conversion circuit. An internal boosted voltage-generating circuit constantly generates a booted voltage which is higher than an externally-applied power supply voltage applied to a power supply terminal. The boosted voltage is applied to the level conversion circuit. The level conversion circuit converts an input control signal, whose high-level voltage is equal to, or lower than the externally-applied power supply voltage, into the boosted voltage, thereby generating the equalization control signal.

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