Reducing power consumption in on-chip memory devices
Wordline driver circuit having an automatic precharge circuit
Semiconductor memory device
Semiconductor memory device with improved bit line precharged circuits
Dynamic random access memory device having precharge circuit for intermittently and selectively charging data line pairs
RAM row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver
Synchronous memory with reduced power access mode
Dynamic random access memory device with low-power consumption column selector
Low power consumption semiconductor memory
ApplicationNo. 828571 filed on 03/31/1997
US Classes:365/203, Precharge365/189.02, Multiplexing365/227, Conservation of power365/230.02, Multiplexing365/230.06Particular decoder or driver circuit
ExaminersPrimary: Nelms, David C.
Assistant: Phan, Trong
Attorney, Agent or Firm
International ClassesG11C 007/00
AbstractA low power RAM device including a bit line precharge circuit which selectively precharges only those bit lines which will be read in an effort to minimize precharge and overall RAM power consumption. The preferred RAM precharge circuit uses a precharge device in the sense amplifier as the primary bit line precharge device to selectively connect and precharge the selected bit line through a column MUX. The preferred RAM precharge also includes secondary bit line precharge devices for each bit line to enable trickle charging thereof to prevent hazardous RAM data corruption. Since RAM corruption occurs only after several clock cycles, the secondary precharge devices comprise small transistors having only 1/20 the size of normal precharge device to conserve precharge power requirements. The RAM device includes a carefully controlled timing sequence of precharge signal, column-select signals, and word-line signals, to selective precharge the selected bit line and to remove the hazardous power consuming DC current path to further reduce power consumption therein.