Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache
January 25, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesComputer assisted display processor having memory sharing by the computer and the processor Cache address comparator with sram having burst addressing control Cache which provides status information Data processing system and method with small fully-associative cache and prefetch buffers Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss Methods and apparatus for providing multiple pending operations in a cache consistent multiple processor computer system Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems Data processor having a cache memory capable of being used as a linear ram bank Cache memory system including a RAM for storing data and CAM cell arrays for storing virtual and physical addresses Real time cache implemented by on-chip memory having standard and cache operating modes Patent #: 5586293 InventorApplicationNo. 591921 filed on 01/25/1996US Classes:711/118, Caching711/138Cache bypassingExaminersPrimary: Swann, Tod R.Assistant: Lee, Felix B. Attorney, Agent or FirmInternational ClassG06F 012/08AbstractA microprocessor architecture including a first cache memory disposed on-chip for storing data along with an associated on-chip tag memory. A second memory is provided on-chip for storing data in a first mode of operation and for storing tags relating to the contents of a second cache memory in a second mode of operation. The mode of operation is set by control logic. The mode is selected by setting a bit in a mode control register. When the bit is set, the control logic changes the system from a first mode in which the second memory serves as additional on-chip cache memory to a second mode in which the second memory stores tags for an external level 2 cache memory. The invention provides a flexible cache structure in which increased on-chip cache is provided or tag memory area is provided for an off-chip level 2 cache.Other References
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