Hardware extraction technique for programmable reduced instruction set computers
Patent 5819064 Issued on October 6, 1998. Estimated Expiration Date: 
November 8, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 8, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSystem and method for compiling a source code supporting data parallel variables Method and apparatus for compiling computer programs with interproceduural register allocation Successive translation, execution and interpretation of computer program having code at unknown locations due to execution transfer instructions having computed destination addresses System for monitoring computer system performance Patent #: 5539907 InventorsAssigneeApplicationNo. 555058 filed on 11/08/1995US Classes:703/27, Compatibility emulation703/21, Computer or peripheral device703/22, Software program (i.e., performance prediction)712/200ARCHITECTURE BASED INSTRUCTION PROCESSINGExaminersPrimary: Trans, Vincent N.Assistant: Mohamed, Ayni Attorney, Agent or FirmInternational ClassG06F 009/45AbstractA new class of purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle.Other References
| |
