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Non-volatile semiconductor memory device capable of high speed programming/erasure

Patent 5818761 Issued on October 6, 1998. Estimated Expiration Date: Icon_subject July 18, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

EPROM source bias circuit with compensation for processing characteristics
Patent #: 5218571
Issued on: 06/08/1993
Inventor: Norris

High-speed memory with a limiter of the drain voltage of the cells
Patent #: 5303189
Issued on: 04/12/1994
Inventor: Devin, et al.

Memory programming load-line circuit with dual slope I-V curve
Patent #: 5398203
Issued on: 03/14/1995
Inventor: Prickett, Jr.

Voltage regulator for non-volatile semiconductor memory devices Patent #: 5576990
Issued on: 11/19/1996
Inventor: Camerlenghi, et al.

Inventors

Application

No. 897101 filed on 07/18/1997

US Classes:

365/185.18, Particular biasing365/185.11, Bank or block architecture365/185.13, Global word or bit lines365/185.24Threshold setting (e.g., conditioning)

Examiners

Primary: Hoang, Huan

Attorney, Agent or Firm

International Class

G11C 016/04

Foreign Application Priority Data

1996-09-10 JP

Abstract

To a column line to which a selected memory cell is connected, a write bias voltage is supplied through a selection gate transistor having different channel conductivity type than the memory cell transistor. Current drivability of the selection gate transistor is adapted to be larger than a leak current of the memory cell and to supply a current smaller than the channel current when a channel is formed in one aspect. When a verifying voltage is applied to the selected word line, a large channel current flows when a channel is formed, potential of a subbit line is changed accordingly, and programming is suppressed. In another aspect, the selection gate transistor serves as a constant current source to make the programming speed of the memory cells constant. Thus distribution of threshold values after programming can be made narrow.

Other References

  • "Novel Electron Injection Method Using . . . with a P-Channel Cell", Ohnakado et al.., IEDM 95, pp. 279-282
  • "A High Programming . . . DINOR Flash Memory", O. Sakamoto et al., 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 222-223
  • "3.3V-Only 16 Mb DINOR Flash Memory", S. Kobayashi et al., 1995 IEEE International Solid-State Circuits Conference, pp. 122-12
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