Patent ReferencesEPROM source bias circuit with compensation for processing characteristics High-speed memory with a limiter of the drain voltage of the cells Memory programming load-line circuit with dual slope I-V curve Voltage regulator for non-volatile semiconductor memory devices Patent #: 5576990 InventorsApplicationNo. 897101 filed on 07/18/1997US Classes:365/185.18, Particular biasing365/185.11, Bank or block architecture365/185.13, Global word or bit lines365/185.24Threshold setting (e.g., conditioning)ExaminersPrimary: Hoang, HuanAttorney, Agent or FirmInternational ClassG11C 016/04Foreign Application Priority Data1996-09-10 JPAbstractTo a column line to which a selected memory cell is connected, a write bias voltage is supplied through a selection gate transistor having different channel conductivity type than the memory cell transistor. Current drivability of the selection gate transistor is adapted to be larger than a leak current of the memory cell and to supply a current smaller than the channel current when a channel is formed in one aspect. When a verifying voltage is applied to the selected word line, a large channel current flows when a channel is formed, potential of a subbit line is changed accordingly, and programming is suppressed. In another aspect, the selection gate transistor serves as a constant current source to make the programming speed of the memory cells constant. Thus distribution of threshold values after programming can be made narrow.Other References
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