Patent ReferencesBit synchronizer Method and apparatus for scheduling and mixing media in a multi-media environment Synchronization system for networked multimedia streams System for facilitating continuous, real-time, unidirectional, and asynchronous intertask and end-device communication in a multimedia data processing system using open architecture data communication modules Patent #: 5625845 InventorsAssigneeApplicationNo. 826560 filed on 04/04/1997US Classes:713/400, SYNCHRONIZATION OF CLOCK OR TIMING SIGNALS, DATA, OR PULSES710/122Physical position bus prioritizationExaminersPrimary: Heckler, Thomas M.Attorney, Agent or FirmInternational ClassG06F 017/00AbstractA method and computer program product for synchronizing processing between two or more data streams (e.g., video and sound input) and for rate matching between two different hardware clocks that may drift with respect to one another (e.g., an originating clock represented in a timestamped data stream versus a clock actually rendering the data) in a system of interconnected software drivers running in kernel mode. The present invention overcomes the coordination complexity and inaccuracies in the prior art by providing a clocking mechanism in a system wherein multiple drivers having input and output connection pin instances are chained together. The clocking mechanism synchronizes between data streams by providing a master clock on an input pin instance of a driver that is used to synchronize with other input pin instances on other drivers and "slave" clocks. Synchronization is achieved through event notification or stream position queries so that corresponding frames of data in separate streams are rendered together (e.g., video frames with corresponding sound track). Rate matching is achieved through monitoring a physical clock progression in comparison with a series of data stream timestamps thereby allowing adjustments to match the different clock rates. A common physical clock (e.g., PC clock) can be used as a reference for a component to translate a particular clock time to a time shared by all components with a minimum of error. | |