Associative memory having separately associable zones
Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses
Extended address generating apparatus and method
Instruction issuing mechanism for processors with multiple functional units
Pipelined data processor capable of decoding and executing plural instructions in parallel
Apparatus and method for permitting reading of data from an external memory when data is stored in a write buffer in the event of a cache read miss
Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions
Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
Method and apparatus for priority selection of commands
ApplicationNo. 858583 filed on 05/19/1997
US Classes:711/156, Status storage711/118, Caching711/144Cache status data bit
ExaminersPrimary: Swann, Tod R.
Assistant: King, Conley B. Jr.
Attorney, Agent or Firm
Foreign Patent References
International ClassG06F 012/00
AbstractA load/store buffer is provided which allows both load memory operations and store memory operations to be stored within it. Memory operations are selected from the load/store buffer for access to the data cache, including cases where the memory operation selected is subsequent in program order to a memory operation which is known to miss the data cache and is stored in the buffer. In this way, other memory operations that may be waiting for an opportunity to access the data cache may make such accesses, while the memory operations that have missed await an opportunity to make a main memory request. Memory operations that have missed are indicated by a miss bit being set, so that the mechanism which selects memory operations to access the data cache may ignore them until they become non-speculative.