Outer loop vectorization
September 1, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesComputer vector register processing Computer vector multiprocessing control Method of developing formal identities and program bases in an optimizing compiler Method for vectorizing and executing on an SIMD machine outer loops in the presence of recurrent inner loops Compilation using two-colored pebbling register allocation method such that spill code amount is invariant with basic block's textual ordering Compiling method for vectorizing multiple do-loops in source program Compile method using copy propagation of a variable Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies Method for representing scalar data dependences for an optimizing compiler Interprocedural slicing of computer programs using dependence graphs InventorsAssigneeApplicationNo. 344236 filed on 11/23/1994US Classes:717/160, Including loop717/150, Loop compiling717/156, Using flow graph717/159Code restructuringExaminersPrimary: Oberley, Alvin E.Assistant: Courtenay, III, St. John Attorney, Agent or FirmInternational ClassG06F 009/45AbstractA system and method for vectorizing a non-innermost loop of a nested loop. Iterative loops of a nested loop are analyzed to determine if they can be vectorized (vector legality). If more than one iterative loop can be vectorized, a selection criteria is applied to select the iterative loop which would provide the most return from vectorization (vector selection).Other References
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