Pattern dependent noise reduction in a digital processing circuit utilizing image circuitry
October 23, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSignal bias remover apparatus Single chip integrated analog-to-digital converter circuit powered by a single voltage potential Delta-Sigma modulator with switch capacitor implementation Pipelined digital filters Enhanced delta modulation encoder Method for reducing effects of electrical noise in an analog-to-digital converter High performance sigma delta based analog modem front end Analog to digital conversion with noise reduction Low noise DAC current source topology Delta-sigma modulator with oscillation detect and reset circuit InventorAssigneeApplicationNo. 735573 filed on 10/23/1996US Classes:341/131, Increasing converter resolution (e.g., dithering)341/118, CONVERTER COMPENSATION708/300FilteringExaminersPrimary: Gaffin, JeffreyAssistant: JeanPierre, Peguy Attorney, Agent or FirmForeign Patent References
International ClassesH03M 001/00H03M 001/36 AbstractA delta-sigma analog/digital converter is provided for operating in the analog domain to generate a digital value that is to be processed by a digital signal processor (DSP) (26) to provide on the output a digital output. Each data node in each processing element in the DSP (26) is mirrored by the way of a corresponding data node in the mirror circuit (36). This results in the addition of noise via a noise adder (28) such that each data node in the main portion of the DSP (26) that can draw current from the power supply during a transition will have a corresponding complement node in the mirror circuit (36). Each data node in the mirror circuit will add noise via a transition drawing current from the power supply whenever the transition does not occur at the corresponding data node in the main portion of the DSP (26). Therefore, di/dt noise will be added for each cycle, regardless of the data pattern. This is effected by insuring that, for each data cycle, each data node undergoes a positive and a negative transition. By using a return-to-zero data stream, i.e., inserting a zero in each cycle at each data node, a positive transition and a negative transition can be during each data cycle.Other References
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