Operand dependency tracking system and method for a processor that executes instructions out of order
May 24, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesOut of order instruction load and store comparison Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched Superscalar risc instruction scheduling Apparatus for pipeline streamlining where resources are immediate or certainly retired Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor Multiple execution unit dispatch with instruction shifting between first and second instruction buffers based upon data dependency Memory conflict buffer for achieving memory disambiguation in compile-time code schedule Patent #: 5694577 InventorsApplicationNo. 653573 filed on 05/24/1996US Classes:712/218, Commitment control or register bypass712/215, Simultaneous issuance of multiple instructions712/217Scoreboarding, reservation station, or aliasingExaminersPrimary: Lall, Parshotam S.Assistant: Patel, Gautam R. International ClassG06F 009/38AbstractAn operand dependency tracking system tracks move-to-space (MTSP) operand dependencies among instructions in a processor that executes instructions out of order. Instructions are forwarded from an instruction fetch mechanism to a reordering mechanism, where the instructions are permitted to execute out of order. After execution of an instruction by an execution unit, instructions are retired by a retire mechanism, which transforms the results of instruction execution to the architecture state. While instructions are executed in the reordering mechanism, the operand dependency tracking system detects an MTSP instruction and a load instruction. The MTSP instruction is destined to modify data in a space register that stores virtual address information. The load instruction is controlled to commence execution after the MTSP instruction commences execution. While executing the load instruction, the tracking system determines whether the load instruction is destined to use the data in the space register. When the load instruction is destined to use the data in the space register, then the tracking system performs the following steps: determines if the MTSP instruction is retired, (2) when the MTSP instruction is not retired, then aborts execution of the load instruction and repeats steps (b) and (d)(1) successively until the MTSP instruction is retired from execution; and (3) when the MTSP instruction is retired, completes execution of the load instruction. Finally, when the load instruction is not destined to use the data in the space register, then the tracking system completes execution of the load instruction regardless of when the MTSP instruction retires from execution.Other References
| |
