Low cost, highly parallel memory tester
Patent 5794175 Issued on August 11, 1998. Estimated Expiration Date: 
September 9, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 9, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3676777 Test pattern generating apparatus Tester for LSI devices and memory devices Solid state multiprobe testing apparatus Distributed pattern generator Automatic test system with enhanced performance of timing generators Method and apparatus for detecting defect on semiconductor substrate surface Semiconductor array having built-in test circuit for wafer level testing Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor Method and system for testing memory programming devices Patent #: 5682472 InventorAssigneeApplicationNo. 926117 filed on 09/09/1997US Classes:702/119, Including program initialization (e.g., program loading) or code selection (e.g., program creation)324/73.1, PLURAL, AUTOMATICALLY SEQUENTIAL TESTS324/158.1, MISCELLANEOUS702/118, Testing multiple circuits714/25, Fault locating (i.e., diagnosis or testing)714/30, Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path)714/718, Memory testing714/724Digital logic testingExaminersPrimary: Arana, LouisAssistant: Bui, Bryan Attorney, Agent or FirmInternational ClassG06F 011/00ClaimsWhat is claimed is: 1. Automatic test equipment for semiconductor devices comprising: a) an array having a plurality of sockets for memory devices under test; b) pattern generator circuitry having a plurality of data lines, a plurality of address lines, a strobe line and an output enable line extending therefrom; c) fanout circuitry comprising: i) a plurality of latches, each having a data input connected to a portion of the plurality of sockets for memory devices under test and a clock input; ii) a plurality of buffer amplifiers connecting the address and data lines to each of the plurality of sockets for memory devices under test; iii) a programmable delay circuit connecting the strobe signal to the clock inputs of the plurality of latches, the programmable delay circuit having a control input; iv) routing circuitry having an input connected to the output enable line and a plurality of outputs, each connected to a portion of the plurality of sockets for memory devices under test, the routing circuitry also having a control input; v) wherein the control input of the programmable delay circuit is coupled to the control input of the routing circuit. 2. The automatic test equipment of claim 1 wherein the array comprises a rectangular array of sockets. 3. The automatic test equipment of claim 1 wherein the array is disposed on a printed circuit board external to the automatic test equipment. 4. The automatic test equipment of claim 3 wherein the array comprises at least 24 sockets. 5. The automatic test equipment of claim 4 additionally comprising at least one other like printed circuit board. 6. The automatic test equipment of claim 1 comprising at least a first printed circuit board, a second printed circuit board, and means for electrically interconnecting the first printed circuit board and the second printed circuit board, wherein the fanout circuitry is disposed on the first printed circuit board and the array is disposed on the second printed circuit board. 7. The automatic test equipment of claim 1 additionally comprising a backplane having at least two sides, with the array mounted on one side of the backplane and the fanout circuitry mounted on a second side of the backplane. 8. Automatic test equipment for semiconductor devices comprising: a) an array having a plurality of sockets for memory devices under test; b) pattern generator circuitry having a plurality of data lines, a plurality of address lines, a strobe line and an output enable line extending therefrom; c) fanout circuitry comprising: i) a plurality of latches, each having a data input connected to a portion of the plurality of sockets for memory devices under test and a latch input, causing the latch to store the data at its input when the latch input is asserted; ii) at least one buffer amplifier, connecting the address and data lines to each of the plurality of sockets for memory devices under test; iii) routing circuitry having an input connected to the output enable line and a plurality of outputs, each connected to a portion of the plurality of sockets for memory devices under test, the routing circuitry also having a control input; iv) wherein the control input of the programmable delay circuit is coupled to the control input of the routing circuit; d) a programmable delay circuit coupling the strobe signal to the latch inputs of the plurality of latches, the programmable delay circuit having a control input, with the control input to the programmable delay circuit being coupled to the control input of the routing circuit. 9. The automatic test equipment of claim 8 wherein the array comprises a rectangular array of sockets, with the sockets disposed in rows in columns, with address and data lines running parallel to the rows of sockets and the plurality of outputs of the routing circuitry run parallel with the columns of sockets. 10. The automatic test equipment of claim 8 wherein the data and address lines are implemented as microstrip transmission lines that are terminated. 11. A method of operating automatic test equipment for semiconductor devices, comprising the steps of: a) loading a plurality of semiconductor memory devices into an array of test sites; b) providing address and data signals to each of the semiconductor memory devices to store data into each of the semiconductor memory devices contemporaneously; c) providing address signals to each of the semiconductor memory devices and selectively providing an output enable signal to portions of the plurality of semiconductor memory devices; d) latching the data read from the memories with a strobe signal that has been delayed in proportion to the physical location of the portion of the plurality of memory devices that received an output enable signal; and e) processing the latched data to detect defects in the semiconductor memory devices. 12. The method of claim 11 wherein the step of loading the plurality of memory devices into an array comprises loading the memory devices into a rectangular array. 13. The method of claim 11 wherein the step of loading the plurality of memory devices into an array comprises loading the plurality of memory devices into a plurality of arrays on separate printed circuit boards and simultaneously processing the semiconductor memory devices on each of the plurality of printed circuit boards. 14. The method of claim 13 additionally comprising, prior to the step of providing address and data signals, the step of loading the semiconductor memory devices in a burn in tester. 15. The method of claim 11 wherein the semiconductor memory devices comprise RAMBUS memories. 16. The method of claim 11 additionally comprising, after the step of providing address and data signals, the step of waiting a retention interval. 17. The method of claim 16 wherein the step of providing address and data signals comprises providing address and data signals at rate that is at least 60 MHz. |
