Low cost, highly parallel memory tester
September 9, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3676777 Test pattern generating apparatus Tester for LSI devices and memory devices Solid state multiprobe testing apparatus Distributed pattern generator Automatic test system with enhanced performance of timing generators Method and apparatus for detecting defect on semiconductor substrate surface Semiconductor array having built-in test circuit for wafer level testing Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor Method and system for testing memory programming devices Patent #: 5682472 InventorAssigneeApplicationNo. 926117 filed on 09/09/1997US Classes:702/119, Including program initialization (e.g., program loading) or code selection (e.g., program creation)324/73.1, PLURAL, AUTOMATICALLY SEQUENTIAL TESTS324/158.1, MISCELLANEOUS702/118, Testing multiple circuits714/25, Fault locating (i.e., diagnosis or testing)714/30, Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path)714/718, Memory testing714/724Digital logic testingExaminersPrimary: Arana, LouisAssistant: Bui, Bryan Attorney, Agent or FirmInternational ClassG06F 011/00AbstractAutomatic test equipment for semiconductor memories that provides testing of large arrays of semiconductor memory chips in parallel. Such massively parallel memory testing greatly enhances test throughput, thereby reducing cost. It greatly enhances the economics of testing memory device made according to a RAMBUS standard, which includes a low speed port and a medium speed port because it allows the same automatic test equipment to economically be used to test devices with the low speed port and the medium speed port. | |
