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US Patent 5794175 - Low cost, highly parallel memory tester
US Patent Issued on August 11, 1998
Estimated Patent Expiration Date:
September 9, 2017Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
September 9, 2017Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractAutomatic test equipment for semiconductor memories that provides testing of large arrays of semiconductor memory chips in parallel. Such massively parallel memory testing greatly enhances test throughput, thereby reducing cost. It greatly enhances the economics of testing memory device made according to a RAMBUS standard, which includes a low speed port and a medium speed port because it allows the same automatic test equipment to economically be used to test devices with the low speed port and the medium speed port. | InventorAssigneeApplicationNo. 926117 filed on 09/09/1997US Classes:702/119, Including program initialization (e.g., program loading) or code selection (e.g., program creation)324/73.1, PLURAL, AUTOMATICALLY SEQUENTIAL TESTS324/158.1, MISCELLANEOUS702/118, Testing multiple circuits714/25, Fault locating (i.e., diagnosis or testing)714/30, Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path)714/718, Memory testing714/724Digital logic testingField of Search324/73.1, PLURAL, AUTOMATICALLY SEQUENTIAL TESTS324/158.1, MISCELLANEOUS324/754, With probe elements324/757, Probe contact enhancement324/763DUT including test circuitExaminersPrimary: Arana, LouisAssistant: Bui, Bryan Attorney, Agent or FirmUS Patent References3676777, 4293950, Test pattern generating apparatusIssued on: 10/06/1981 Inventor: Shimizu , et al.4450560, Tester for LSI devices and memory devices Issued on: 05/22/1984 Inventor: Conner4585991, Solid state multiprobe testing apparatus Issued on: 04/29/1986 Inventor: Reid , et al.4639919, Distributed pattern generator Issued on: 01/27/1987 Inventor: Chang , et al.4806852, Automatic test system with enhanced performance of timing generators Issued on: 02/21/1989 Inventor: Swan , et al.5271796, Method and apparatus for detecting defect on semiconductor substrate surface Issued on: 12/21/1993 Inventor: Miyashita, et al.5457400, Semiconductor array having built-in test circuit for wafer level testing Issued on: 10/10/1995 Inventor: Ahmad, et al.5617531, Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor Issued on: 04/01/1997 Inventor: Crouch, et al.5682472Method and system for testing memory programming devices Issued on: 10/28/1997 Inventor: Brehm, et al. International ClassG06F 011/00 |
