U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Low cost, highly parallel memory tester

Patent 5794175 Issued on August 11, 1998. Estimated Expiration Date: Icon_subject September 9, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

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Inventor

Assignee

Application

No. 926117 filed on 09/09/1997

US Classes:

702/119, Including program initialization (e.g., program loading) or code selection (e.g., program creation)324/73.1, PLURAL, AUTOMATICALLY SEQUENTIAL TESTS324/158.1, MISCELLANEOUS702/118, Testing multiple circuits714/25, Fault locating (i.e., diagnosis or testing)714/30, Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path)714/718, Memory testing714/724Digital logic testing

Examiners

Primary: Arana, Louis
Assistant: Bui, Bryan

Attorney, Agent or Firm

International Class

G06F 011/00

Abstract

Automatic test equipment for semiconductor memories that provides testing of large arrays of semiconductor memory chips in parallel. Such massively parallel memory testing greatly enhances test throughput, thereby reducing cost. It greatly enhances the economics of testing memory device made according to a RAMBUS standard, which includes a low speed port and a medium speed port because it allows the same automatic test equipment to economically be used to test devices with the low speed port and the medium speed port.

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