Patent ReferencesCommand delivery for a computing system for transfers between a host and subsystem including providing direct commands or indirect commands indicating the address of the subsystem control block Multi-processor communications channel utilizing random access/sequential access memories System for asynchronously delivering self-describing control elements with a pipe interface having distributed, shared memory Bridge interface between two buses of a computer system with a direct memory access controller programmed by a scatter/gather programmer Apparatus for a multiple channel direct memory access utilizing a virtual array technique Programmably configurable host adapter integrated circuit including a RISC processor Patent #: 5659690 InventorsApplicationNo. 572265 filed on 12/13/1995US Classes:710/2, Input/Output expansion709/215, Partitioned shared memory710/20, Concurrent Input/Output processing and data transfer710/36, Input/Output access regulation711/163Access limitingExaminersPrimary: Chan, Eddie P.Assistant: Kim, Chong H. International ClassesG06F 013/00G06F 013/14 AbstractAn information handling system transfers data blocks between a host processing side having a CPU and a host memory and a local processing side having a local processing unit and a local memory. The local memory includes a DCB queue memory portion having a plurality of DCB images each image defining host and local addresses of a corresponding data transfer. The DCB images also store a default status condition representing the most likely condition of a data transfer which in the preferred embodiment is a no error condition. A data transfer status detector determines whether the default status condition is true or false. If true, the default status information relating to a corresponding data block transfer is posted on the host processing side without local processing unit intervention.Field of SearchAccess limiting | |